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LTC694-3.3/LTC695-3.3 3.3V Microprocessor Supervisory Circuits
FEATURES
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DESCRIPTIO
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s s s s s s
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Guaranteed Reset Assertion at VCC = 1V Pin Compatible with LTC694/LTC695 for 3.3V Systems 200A Typical Supply Current Fast (30ns Typ) On-Board Gating of RAM Chip Enable Signals SO-8 and SO-16 Packages 2.90V Precision Voltage Monitor Power OK/Reset Time Delay: 200ms or Adjustable Minimum External Component Count 1A Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature
The LTC694-3.3/LTC695-3.3 provide complete 3.3V power supply monitoring and battery control functions. These include power-on reset, battery backup, RAM write protection, power failure warning and watchdog timing. The devices are pin compatible upgrades of the LTC694/ LTC695 that are optimized for 3.3V systems. Operating power consumption has been reduced to 0.6mW (typical) and 3W maximum in battery backup mode. Microprocessor reset and memory write protection are provided when the supply falls below 2.9V. The RESET output is guaranteed to remain logic low with VCC as low as 1V. The LTC694-3.3/LTC695-3.3 power the active RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC694-3.3/LTC695-3.3 provide an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period.
APPLICATI
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S
3.3V Low Power Systems Critical P Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems
TYPICAL APPLICATI
VIN 5V
+
1F
LT1129-3.3 VIN VOUT OUT SENSE SHDN GND
3.3V
+
100F 0.1F
VCC
VOUT
LTC695-3.3 VBATT CE IN CE OUT RESET PFO GND WDI
RESET OUTPUT VOLTAGE (V)
2.4V 51k PFI 18k MICROPROCESSOR RESET, BATTERY BACKUP, RAM WRITE PROTECTION, POWER WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR 3.3V MICROPROCESSOR SYSTEM.
POWER TO P CMOS RAM POWER 0.1F P SYSTEM DECODER OUTPUT RAM CS P RESET P NMI I/O LINE 100 0.1F
694/5-3.3 TA01
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RESET Output Voltage vs Supply Voltage
5 4 3 2 1 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5
694/5-3.3 TA02
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1
LTC694-3.3/LTC695-3.3 ABSOLUTE AXI U RATI GS (Notes 1 and 2)
VOUT Output Current ................. Short-Circuit Protected Power Dissipation............................................. 500mW Operating Temperature Range LTC694C-3.3/LTC695C-3.3 .................. 0C to 70C LTC694I-3.3/LTC695I-3.3 ............... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
Terminal Voltage VCC ...................................................... - 0.3V to 6V VBATT ................................................... - 0.3V to 6V All Other Inputs .................. - 0.3V to (VOUT + 0.3V) Input Current VCC .............................................................. 100mA VBATT ............................................................. 25mA GND .............................................................. 10mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VBATT VOUT VCC GND BATT ON LOW LINE OSC IN OSC SEL 1 2 3 4 5 6 7 8 LTC695-3.3 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT
ORDER PART NUMBER LTC695CN-3.3 LTC695IN-33
11 WDI 10 PFO 9 PFI
N PACKAGE 16-LEAD PLASTIC DIP
TJMAX = 110C, JA = 130C/W
TOP VIEW VOUT VCC GND 1 2 LTC694-3.3 3 6 5 8 7 VBATT RESET WDI PFO
LTC694CN-3.3 LTC694IN-3.3
PFI 4
N8 PACKAGE 8-LEAD PLASTIC DIP
TJMAX = 110C, JA = 130C/W
PRODUCT SELECTIO GUIDE
PINS LTC694-3.3 LTC695-3.3 LTC690 LTC691 LTC694 LTC695 LTC699 LTC1232 LTC1235 8 16 8 16 8 16 8 8 16 RESET THRESHOLD (V) 2.90 2.90 4.65 4.65 4.65 4.65 4.65 4.37/4.62 4.65 WATCHDOG TIMER X X X X X X X X X BATTERY BACKUP X X X X X X POWER FAIL WARNING X X X X X X X X X X X RAM WRITE PROTECT PUSHBUTTON RESET CONDITIONAL BATTERY BACKUP
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WW
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(Note 3)
TOP VIEW VBATT 1 VOUT 2 VCC 3 GND 4 BATT ON 5 LOW LINE 6 OSC IN 7 OSC SEL 8 LTC695-3.3 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT 11 WDI 10 PFO 9 PFI S PACKAGE 16-LEAD PLASTIC SOL
ORDER PART NUMBER LTC695CS-3.3 LTC695IS-3.3
TJMAX = 110C, JA = 130C/W
TOP VIEW VOUT VCC GND PFI 1 2 3 4 LTC694-3.3 8 7 6 5 VBATT RESET WDI PFO
LTC694CS-3.3 LTC694IS-3.3 S8 PART MARKING 694 694I
S8 PACKAGE 8-LEAD PLASTIC SOIC
TJMAX = 110C, JA = 180C/W
X
X
X
X
LTC694-3.3/LTC695-3.3
ELECTRICAL CHARACTERISTICS
VCC = 3.3V, VBATT = 2V, TA = 25C, unless otherwise noted.
PARAMETER Battery Backup Switching Operating Voltage Range VCC VBATT VOUT Output Voltage IOUT = 1mA
q q q
CONDITIONS
MIN
TYP
MAX
UNITS
3.0 1.5 VCC - 0.1 VCC - 0.2 VCC - 0.8 VBATT - 0.1 VCC - 0.01 VCC - 0.01 VCC - 0.4 VBATT - 0.02 0.2 0.2 0.04 0.04 - 0.02 - 0.10 70 50 20
5.50 2.75
V V V V V V
IOUT = 50mA VOUT in Battery Backup Mode Supply Current (Exclude IOUT) Supply Current in Battery Backup Mode Battery Standby Current (+ = Discharge, - = Charge) Battery Switchover Threshold (VCC - VBATT) Battery Switchover Hysteresis BATT ON Output Voltage (Note 4) BATT ON Output Short-Circuit Current (Note 4) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time Watchdog Time-Out Period, Internal Oscillator OSC SEL HIGH, VCC = 3V ISINK = 800A BATT ON = VOUT, Sink Current BATT ON = 0V, Source Current IOUT = 250A, VCC < VBATT IOUT 50mA, VCC = 3.6V
q q q
0.6 1.0 1 5 0.02 0.10
mA mA A A A A mV mV mV
VCC = 0V, VBATT = 2V
q
3.6V > VCC > VBATT + 0.2V
q
Power Up Power Down
q q
0.3 0.5 25 1 25
V mA A
q
2.8
2.9 40
3.0
V mV
q
160 140 1.2 1.0 80 70 4032 960
200 200 1.6 1.6 100 100
240 280 2.0 2.25 120 140 4097 1025
ms ms sec sec ms ms Clock Cycles ms/V ms/V ms/V ns
Long Period, VCC = 3V
q
Short Period, VCC = 3V
q
Watchdog Time-Out Period, External Clock (Note 5) Reset Active Time PSRR Watchdog Time-Out Period PSRR, Internal OSC Minimum WDI Input Pulse Width RESET Output Voltage at VCC = 1V RESET and LOW LINE Output Voltage (Note 4) RESET and WDO Output Voltage (Note 4) RESET, RESET, WDO, LOW LINE Output Short-Circuit Current (Note 4)
Long Period, VCC = 3V Short Period, VCC = 3V Short Period Long Period VIL = 0.4V, VIH = 3V ISINK = 10A, VCC = 1V ISINK = 400A, VCC = 2.8V ISOURCE = 1A, VCC = 3V ISINK = 400A, VCC = 3V ISOURCE = 1A, VCC = 2.8V Output Source Current Output Sink Current
q q
4 2 32
q q q q q q q
200 4 2.3 0.3 2.3 1 3 9 25 200 0.3
mV V V V V A mA
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LTC694-3.3/LTC695-3.3
ELECTRICAL CHARACTERISTICS
VCC = 3.3V, VBATT = 2V, TA = 25C, unless otherwise noted.
PARAMETER WDI Input Threshold WDI Input Current Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR PFI Input Current PFO Output Voltage (Note 4) PFO Short-Circuit Source Current (Note 4) PFI Comparator Response Time (Falling) PFI Comparator Response Time (Rising) (Note 4) Chip Enable Gating CE IN Threshold CE IN Pullup Current (Note 6) CE OUT Output Voltage ISINK = 800A ISOURCE = 400A ISOURCE = 1A, VCC = 0V CL = 20pF Output Source Current Output Sink Current
q q q q q q
CONDITIONS Logic Low Logic High WDI = VOUT WDI = 0V
q q q q
MIN 2.3 - 50
TYP
MAX 0.4
UNITS V V A A
4 -8
50
1.25
1.3 0.3 0.01
1.35
V mV/V
25 0.3
nA V V A mA s s s
ISINK = 800A ISOURCE = 1A PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT VIN = - 20mV, VOD = 15mV VIN = 20mV, VOD = 15mV with 10k Pullup
q q q
2.3 1 3 17 2 40 8 25
VIL VIH
0.45 1.9 3 0.3 VOUT - 0.50 VOUT - 0.05 30 15 20 2 5 50
V V A V V V ns mA mA A A
CE IN Propagation Delay CE OUT Output Short-Circuit Current Oscillator OSC IN Input Current (Note 6) OSC SEL Input Pullup Current (Note 6) OSC IN Frequency Range
OSC SEL = 0V OSC SEL = 0V, COSC = 47pF
q
0 4
125
kHz kHz
The q denotes specifications which apply over the operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pullups of typically 3A. However, external pullup resistors may be used when higher speed is required.
Note 5: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer. Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 plus one clock of jitter. Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal pullups which pull to the supply when the input pins are floating.
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LTC694-3.3/LTC695-3.3
TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage vs Load Current
3.30 3.25 OUTPUT VOLTAGE (V) 3.20 SLOPE = 4.6 3.15 3.10 3.05 3.00 0 10 30 40 20 LOAD CURRENT (mA) 50 VCC = 3.3V VBATT = 2.4V TA = 25C
OUTPUT VOLTAGE (V)
PFI INPUT THRESHOLD (V)
Power Fail Comparator Response Time
PFO OUTPUT VOLTAGE (V)
3.5
PFO OUTPUT VOLTAGE (V)
3.0 2.5 2.0 1.5 1.0 0.5 0
VPFI 1.3V + -
3.0 2.5 2.0 1.5 1.0 0.5 0
PFO OUTPUT VOLTAGE (V)
VCC = 3.3V TA = 25C
1.305V 1.285V 0 1
VPFI = 20mV STEP
2
345 TIME (s)
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Reset Active Time vs Temperature
220 VCC = 3.3V
RESET VOLTAGE THRESHOLD (V)
210
RESET ACTIVE TIME (ms)
200 190 180 170 160 150 -50 -25
2.88 2.87 2.86 2.85 2.84 -50 -25
RESET OUTPUT VOLTAGE (V)
50 25 75 0 TEMPERATURE (C)
UW
694/5-3.3 G01
Output Voltage vs Load Current
2.40 VCC = 0V VBATT = 2.4V TA = 25C
1.310 1.308 1.306 1.304 1.302 1.300 1.298 1.296
Power Failure Input Threshold vs Temperature
VCC = 3.3V
2.39
2.38 SLOPE = 90 2.37
2.36
2.35 0 100 300 400 200 LOAD CURRENT (A) 500
1.294 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
694/5-3.3 G02
694/5-3.3 G03
Power Fail Comparator Response Time
3.5 VCC = 3.3V TA = 25C
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.315V 1.295V
Power Fail Comparator Response Time with Pullup Resistor
VCC = 3.3V TA = 25C
PFO 30pF
VPFI 1.3V
+ - PFO 30pF
3.3V VPFI 1.3V + - 10k PFO 30pF
1.315V 1.295V
VPFI = 20mV STEP 0 20 40 60 80 100 120 140 160 180 TIME (s)
694/5-3.3 G05
VPFI = 20mV STEP 0 2 4 6 8 10 12 14 16 18 TIME (s)
694/5-3.3 G06
7
8
9
694/5-3.3 G04
Reset Voltage Threshold vs Temperature
2.90 VCC = 3.3V 2.89
4 3 5
RESET Output Voltage vs Supply Voltage
2
1
100
125
50 25 75 0 TEMPERATURE (C)
100
125
0
0
1
3 4 2 SUPPLY VOLTAGE (V)
5
694/5-3.3 TA02
694/5-3.3 G07
694/5-3.3 G08
5
LTC694-3.3/LTC695-3.3
PI FU CTIO S
VCC: 3.3V Supply Input. The VCC pin should be bypassed with a 0.1F capacitor. VOUT: Voltage Output for Backed Up Memory. Bypass with a capacitor of 0.1F or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical on resistance of 5. When VCC is lower than VBATT, VOUT is internally switched to VBATT. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Backup Battery Input. When VCC falls below VBATT, auxiliary power connected to VBATT, is delivered to VOUT through PMOS switch, M2. If backup battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground Pin. BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 25mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the power fail comparator, C3. The inverting input is internally connected to a 1.3V reference. The power failure output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. RESET: Logic Output for P Reset Control. Whenever VCC falls below either the reset voltage threshold (2.90V, typically) or VBATT, RESET goes active low. After VCC returns to 3.3V, the reset pulse generator forces RESET to remain active low for a minimum of 140ms. When the watchdog timer is enabled but not serviced prior to a preset time-out period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for every preset time-out period (see Figure 11). The reset active time is adjustable on the LTC695-3.3. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in Applications Information section. RESET: Active High Logic Ouput. It is the inverse of RESET. LOW LINE: Logic Output from Comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (2.90V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1). WDI: Watchdog Input. WDI is a three-level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the watchdog timer. The timer resets itself with each transition of the watchdog input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information section and Figure 5 for additional information. CE OUT: Logic Output on the Chip Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5). OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low, allows OSC IN to be driven from an external clock signal or an external capacitor can be connected between OSC IN and GND.
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LTC694-3.3/LTC695-3.3
PI FU CTIO S
OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical for the LTC695-3.3. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases, the time-out period immediately after a reset is 1.6 seconds typical.
BLOCK DIAGRA
VBATT VCC
CE IN - C3 +
PFI OSC IN OSC OSC SEL
WDI
W
U
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M2 M1
VOUT
CHARGE PUMP - C2 + LOW LINE + C1 - 1.3V BATT ON
CE OUT
GND
PFO RESET RESET PULSE GENERATOR RESET WATCHDOG TIMER WDO
694/5-3.3 BD
TRANSITION DETECTOR
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LTC694-3.3/LTC695-3.3
APPLICATI
S I FOR ATIO
Microprocessor Reset The LTC694-3.3/LTC695-3.3 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the 3.3V supply input on VCC (see Block Diagram). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 3.0V (2.9V typical). On power-up, the RESET signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to
V2 VCC V1
RESET
t1
LOW LINE
694/5-3.3 F01
Figure 1. Reset Active Time
stabilize. The reset active time is adjustable on the LTC6953.3. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the RESET output. Response time is typically 10s. To help prevent mistriggering due to transient loads, the VCC pin should be bypassed with a 0.1F capacitor with the leads trimmed as short as possible. The LTC695-3.3 has two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold.
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Battery Switchover The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a chargepumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20s.
V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 t1 t1 = RESET ACTIVE TIME
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During normal operation, the LTC694-3.3/LTC695-3.3 use a charge-pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5. The VOUT pin should be bypassed with a capacitor of 0.1F or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC - VOUT voltage differential) is desired, the LTC695-3.3 should be used. This product provides BATT ON output to drive the base of an external PNP transistor (Figure 2). If higher currents are needed with the LTC694-3.3, a high current Schottky diode can be connected from the VCC pin to the VOUT pin to supply the extra current.
LTC694-3.3/LTC695-3.3
APPLICATI
S I FOR ATIO
ANY PNP POWER TRANSISTOR
5 3.3V 3 0.1F 1 2.4V BATT ON 2 VOUT VCC LTC695-3.3 VBATT GND 4
694/5-3.3 F02
0.1F
Figure 2. Using BATT ON to Drive External PNP Transistor
The LTC694-3.3/LTC695-3.3 are protected for safe area operation with short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155C with about 10C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC694-3.3/LTC695-3.3 use a chargepumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by VBATT pin is strictly junction leakage. A 125 PMOS switch connects the VBATT input to VOUT in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is 1A maximum. The operating voltage at the VBATT pin ranges from 1.5V to 2.75V. The charging resistor for rechargeable batteries should be connected to VOUT since this eliminates the discharge path that exists when the resistor is connected to VCC (Figure 3).
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I= R 3.3V 0.1F LTC694-3.3 LTC695-3.3 VBATT GND VCC VOUT 0.1F VOUT - VBATT R 2.4V
694/5-3.3 F03
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Figure 3. Charging External Battery Through VOUT
Replacing the Backup Battery When changing the backup battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC694-3.3/LTC695-3.3 switch to battery backup. VOUT pulls VBATT low and the device goes back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1A maximum over temperature so the external resistor required to hold VBATT below VCC is:
V - 50mV R CC 1A
With VCC = 3V, a 2.7M resistor will work. With a 2V battery, this resistor will draw only 0.7A from the battery, which is negligible in most cases. If battery connections are made through long wires, a 10 to 100 series resistor and a 0.1F capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4).
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LTC694-3.3/LTC695-3.3
APPLICATI
S I FOR ATIO
VBATT 0.1F LTC694-3.3 LTC695-3.3
10 2.7M
GND
694/5-3.3 F04
Figure 4. 10/0.1F combination eliminates inductive overshoot and prevents spurious resets during battery replacement. The 2.7M pulls the VBATT pin to ground while the battery is removed, eliminating spurious resets.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL VCC VOUT VBATT BATT ON PFI PFO RESET RESET STATUS C2 monitors VCC for active switchover. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1A maximum. Logic high. The open-circuit output voltage is equal to VOUT. Power Failure Input is ignored. Logic low Logic low Logic high. The open-circuit output voltage is equal to VOUT.
LOW LINE Logic low WDI Watchdog Input is ignored. WDO CE IN CE OUT OSC IN OSC SEL Logic high. The open-circuit output voltage is equal to VOUT. Chip Enable Input is ignored. Logic high. The open-circuit output voltage is equal to VOUT. OSC IN is ignored. OSC SEL is ignored.
VCC
CE IN
CE OUT VOUT = VBATT
Figure 5. Timing Diagram for CE IN and CE OUT
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Table 1 shows the state of each pin during battery backup. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Memory Protection The LTC695-3.3 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT follows CE IN with a typical propagation delay of 30ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor's address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC6943.3 by using RESET as shown in Figure 7. Power Fail Warning The LTC694-3.3/LTC695-3.3 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by
V1 V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS VOUT = VBATT
694/5-3.3 F05
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LTC694-3.3/LTC695-3.3
APPLICATI
3.3V 0.1F VCC
S I FOR ATIO
+
10F 0.1F
VOUT
LTC695-3.3 CE OUT VBATT CE IN RESET RESET
CS 30ns PROPAGATION DELAY FROM DECODER
2.4V GND
TO P
Figure 6. A Typical Nonvolatile CMOS RAM Application
3.3V 0.1F
VCC
VOUT
+
VCC 10F 0.1F CS 62128 RAM CS1 CS2 GND
LTC694-3.3 VBATT 2.4V RESET GND
Figure 7. Write Protect for RAM with LTC694-3.3
VIN 5V
+
10F R1 51k
LT1129-3.3 VIN VOUT OUT SENSE SHDN ADJ
3.3V
+
VCC LTC694-3.3 LTC695-3.3 PFO PFI GND
100F R3 200k
0.1F R4 10k
R2 16k
TO P
694/5-3.3 F08
Figure 8. Monitoring Unregulated DC Supply with the LTC694-3.3/LTC695-3.3's Power Fail Comparator
VIN 6.5V
+
LT1129-3.3 VIN VOUT OUT SENSE SHDN ADJ
10F
3.3V R1 27k R4 10k R3 2.7M
0.1F VCC LTC694-3.3 LTC695-3.3 PFO PFI GND TO P
10F
+
R2 16k R5 5k
Figure 9. Monitoring Regulated DC Supply with the LTC694-3.3/LTC695-3.3's Power Fail Comparator
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VCC 62512 RAM GND
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comparing the power failure input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 3.3V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V several milliseconds before the 3.3V supply falls below the maximum reset voltage threshold 3.0V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET. The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin.
694/5-3.3 F06
694/5-3.3 F07
R1 R1 VH =1.3V 1+ + R2 R3
When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction.
R1 (3.3V - 1.3V)R1 VL = 1.3V 1 + - R2 1.3V(R3 + R4)
Assuming R4 << R3,VHYSTERESIS = 3.3 V R1 R3
694/5-3.3 F09
Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 5V which is 1.6V greater than the sum of maximum reset voltage threshold and the dropout voltage of the LT1129-3.3 (3V + 0.4V) and VHYSTERESIS = 850mV.
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LTC694-3.3/LTC695-3.3
APPLICATI
R3 3.88 R1 Choose R3 = 200k and R1 = 51k. Also select R4 = 10k which is much smaller than R3.
2.4V
S I FOR ATIO
R1 = 850mV R3
VHYSTERESIS = 3.3V
51k (3.3V - 1.3V)51k 5V =1.3V 1+ - R2 1.3V(210 k)
R2 = 15.8k, Choose nearest 5% resistor 16k and recalculate VL,
51k (3.3V - 1.3V)51k VL = 1.3V 1 + - = 4.96 V 16k 1.3V(210k)
51k 51k VH = 1.3V 1 + + = 5.77 V 16 k 2 00k
(4.96V - 3.4V) = 15.6ms 100mV/ms VHYSTERESIS = 5.77V - 4.96V = 810mV The 15.6ms allows enough time to execute shutdown procedure for microprocessor and 810mV of hysteresis would prevent PFO from going low due to the noise of VIN. Example 2: The circuit in Figure 9 can be used to measure the regulated 3.3V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 3.1V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.
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3.3V VCC PFO LTC695-3.3 PFI R2 1.6M CE OUT RL 20k OPTIONAL TEST LOAD
694/5-3.3 F10
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VBATT R1 1M
LOW BATTERY SIGNAL TO P I/O PIN
CE IN GND
I/O PIN
Figure 10. Backup Battery Monitor with Optional Test Load
Watchdog Timer The LTC694-3.3/LTC695-3.3 provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the watchdog input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 140ms. The reset active time is adjustable on the LTC695-3.3. Since many systems can not service the watchdog timer immediately after a reset, the LTC695-3.3 has a longer time-out period (1.0 second minimum) right after a reset is issued. The normal timeout period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at 1.0 second minimum on the LTC694-3.3. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog time can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT.
LTC694-3.3/LTC695-3.3
APPLICATI
S I FOR ATIO
VCC = 3.3V WDI
WDO
t2 RESET t1 t1
Figure 11. Watchdog Time-Out Period and Reset Active Time
EXTERNAL CLOCK 3.3V 3 VCC OSC SEL 8 3.3V 3 EXTERNAL OSCILLATOR VCC OSC SEL 8
LTC695-3.3 7 4
4
GND
OSC IN
INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG 3.3V 3 VCC OSC SEL 8 FLOATING OR HIGH 3.3V
LTC695-3.3 4 7 FLOATING OR HIGH 4
GND
OSC IN
Figure 12. Oscillator Configurations
The LTC695-3.3 provides an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT. The LTC695-3.3 has two additonal pins, OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12.
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t1 = RESET ACTIVE TIME t2 = NORMAL WATCHDOG TIME-OUT PERIOD t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A RESET t3
694/5-3.3 F11
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LTC695-3.3 7 OSC IN
GND
INTERNAL OSCILLATOR 100ms WATCHDOG 3 VCC OSC SEL 8 FLOATING OR HIGH
LTC695-3.3 7
GND
OSC IN
694/5-3.3 F12
OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 140ms minimum for the LTC695-3.3. OSC IN selects between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second.
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LTC694-3.3/LTC695-3.3
APPLICATI S I FOR ATIO
Table 2. LTC695-3.3 Reset Active Time and Watchdog Time-Out Selections WATCHDOG TIME-OUT PERIOD OSC SEL
Low Low Floating or High Floating or High
OSC IN
External Clock Input External Capacitor* Low Floating or High
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is FOSC (Hz) = 184,000 C(pF)
Pushbutton Reset The LTC694-3.3/LTC695-3.3 do not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 100 resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1F capacitor to the RESET pin debounces the pushbutton input. The 100 resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC69X below ground.
3.3V VCC RESET 0.1F 100 RESET MPU (e.g. 68HC05)
TYPICAL APPLICATI
S
Capacitor Backup with 74HC4016 Switch
R1 10k 1 R2 30k
10 11 12 14 74HC4016 7 13 100F 2
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RESET ACTIVE TIME LTC695-3.3
2048 CLKs 800ms xC 47pF 200ms 200ms
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NORMAL (Short Period)
1024 CLKs 400ms xC 47pF 100ms 1.6 sec
IMMEDIATELY AFTER RESET (Long Period)
4096 CLKs 1.6 sec xC 47pF 1.6 sec 1.6 sec
LTC694-3.3 LTC695-3.3 GND
694/5-3.3 F13
Figure 13. The External Pushbutton Reset
3.3V VCC 0.1F LTC695-3.3 VBATT LOW LINE VOUT 0.1F
+
GND
694/5-3.3 TA03
LTC694-3.3/LTC695-3.3
TYPICAL APPLICATI UO S
Write Protect for Additional RAMs
0.1F 3.3V 0.1F VCC VOUT LTC695-3.3 CE OUT VBATT 2.4V CE IN LOW LINE GND 0.1F VCC LH5116S RAMB CS1 CS2 0.1F VCC LH5116S RAMC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs
694/5-3.3 TA04
+
10F
VCC LH5168SH RAMA CS
30ns PROPAGATION DELAY CSA
CSB
CSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC694-3.3/LTC695-3.3
PACKAGE DESCRIPTIO
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.016 - 0.050 0.406 - 1.270
0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157 (3.810 - 3.988)
0- 8 TYP
0.014 - 0.019 (0.355 - 0.483)
0.300 - 0.320 (7.620 - 8.128)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN 1 2 3 4
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
0.300 - 0.325 (7.620 - 8.255)
0.130 0.005 (3.302 0.127)
0.009 - 0.015 (0.229 - 0.381)
0.015 (0.381) MIN
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.125 (3.175) MIN
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
0.291 - 0.299 (7.391 - 7.595) 0.005 (0.127) RAD MIN
0.010 - 0.029 x 45 (0.254 - 0.737)
0.093 - 0.104 (2.362 - 2.642)
0 - 8 TYP 0.050 (1.270) TYP
0.009 - 0.013 (0.229 - 0.330)
SEE NOTE 0.016 - 0.050 (0.406 - 1.270)
NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP
8
0.189 - 0.197 (4.801 - 5.004) 7 6 5
0.050 (1.270) BSC 1 2 3 4
SO8 0392
S8 Package 8-Lead Plastic SOIC
0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 8 0.400 (10.160) MAX 7 6 5
0.250 0.010 (6.350 0.254)
0.018 0.003 (0.457 0.076)
N8 0392
N Package 16-Lead Plastic DIP
0.045 - 0.065 (1.143 - 1.651)
0.770 (19.558) MAX 16 15 14 13 12 11 10 9
0.065 (1.651) TYP
0.260 0.010 (6.604 0.254)
1 0.018 0.003 (0.457 0.076)
2
3
4
5
6
7
8
N16 0492
SO Package 16-Lead SOL
16 0.037 - 0.045 (0.940 - 1.143) 15
0.398 - 0.413 (10.109 - 10.490) 14 13 12 11 10 9
SEE NOTE 0.004 - 0.012 (0.102 - 0.305)
0.394 - 0.419 (10.007 - 10.643)
0.014 - 0.019 (0.356 - 0.482) TYP
1
2
3
4
5
6
7
8
SOL16 0392
LT/GP 0293 10K REV 0
(c) LINEAR TECHNOLOGY CORPORATION 1993

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